Synopsys: Assessing ESD Sensitivity of Interface IP Using Charged Device Model

January 11, 2017 // By Peter C. de Jong
An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, especially from the completion of the silicon wafer processing to when the device is assembled in the system. due to the rapid growth in automated handling, manufacturing and assembly of electronic devices, the Charged Device Model (CDM) has become the primary real world ESD event model. This white paper describes the CDM ESD event and explains how IC designers can obtain actual CDM voltage levels of an SoC using the peak current level measured during the interface IP CDM qualification phase.
ESD, electrostatic discharge, IP, design, model