Clock jitter is a parameter which affects system performance and can degrade otherwise superior component specifications. This article is a basic explanation of clock jitter and some of its effects, especially with respect to a phase lock loop (PLL).
At a very fundamental level, jitter is defined as the variation of a signal (in this case a clock output) from its ideal position in time, Figure 1 .
Figure 1.Basic definition of jitter aspects
In an IC, a PLL (frequency synthesizer) is typically used to generate the clocks.
Jitter in clocks has two different components which arise due to various sources.
(a) Random jitter (Rj). Rj arises due to thermal noise inherent in the system and exhibits a etermin distribution. Since Rj is unbounded it is characterized by its rms value. In a PLL, the low frequency RJ typically comes from the reference clock and Charge pump whereas the high frequency jitter is more a manifestation of the VCO thermal noise.
(b) Determinstic jitter (Dj). Dj arises due to eterministic components. Examples include: PLL reference freedthrough, Power supply noise etc. Unlike data, there is no Intersymbol interference (ISI) term. Dj is bounded and specified as a peak number
This deviation from its ideal position can negatively impact data transmission between two clocked elements on-chip as well as off-chip. Example of on-chip systems includes timing violations between two flip flops.
Example of off-chip systems include a Serdes I/O (serializer/deserializer) link where data is sent over long traces of FR4 PC-board substrate. Excessive high-frequency jitter on the clock used for transmitting the data can cause eye closure and excessive bit errors (bit error rate, or BER). In either case different types of clock jitter cause the errors mentioned above.Hence it is critical to understand what type of jitter is important for ones application and how to measure/analyze them.
Jitter Measurements–time and frequency interplay
Jitter can be measured in two different