National's 3.6 GSPS ADC12D1800 claims to be 3.6 times faster than any other available 12-bit ADC.      

The new ADC's dynamic performance of -147 dBm/Hz noise floor, 52 dB noise power ratio (NPR) and -61 dBFS intermodulation distortion (IMD) is designed to enable a new generation of software-defined radio (SDR) architectures and applications.      

In this news analysis article EE Times Europe Analog's editor, Paul Buckley finds out more about the industry's fastest 12-bit analog-to-digital converter (ADC) by interviewing Paul McCormack who is the marketing manager for National's High-speed product group.  


EE TIMES: What is so special about this new analog-to-digital converter development?

McCormack: What we are launching is a family of ultra-high speed 12-bit analog-to-digital converters (ADC).  The fastest device is capable of running sample rates up to 3.6 GSPS in single channel mode.  The device is actually giving us a leadership position in the market with the fastest 12-bit devices which are 3.6 times faster than our competition. This allows us to sample the Nyquist bandwidth 3.6 times higher than the competition can achieve.  The new ADC really is enabling new applications in software-defined radio (SDR) and advances in other new architectures.    

EE Times: How long has National been developing this new ADC?

McCormack: We have been developing these converters for ten years.  We have created 8-bit and 10-bit products in the past and this is an extension of that family going to the next level in terms of sample speed and dynamic range.  We have really pushed the limits and this is the fastest product that you will be able to find on the market.  It is the highest resolution at the fastest sampling speed.    You can run it as a dual channel to take advantage of the two ADC cores.  For example you can run the two ADC cores at 1.8 GSPS and have a two-channel ADC or you can run it as single channel at double that speed.  The interleaving is done on shift and it allows you to sample either the I or Q in single channel mode at up 3.6 GSPS.    


EE TIMES: What are the key benefits of the new ADC?

McCormack: The new 12-bit ADC enables new architectures.  Software-defined radio is a broad term.  Its kind like a digital radio because its more configurable and you can configure the radio digitally with software which adds a lot more flexibility than a traditional approach.  To make a software radio you need a very wide bandwidth and a very fast sampling ADC and this is why we can enable this type of application with the new device.

As for the term software radio - well we call it radio but it can really be any system which is sampling a wide bandwidth of information signals whether that is in mobile communications or TV signals of optical communication systems.  Essentially it suits any system that is dealing with a wide bandwidth of information and requires a high-speed ADC.      

Traditionally, the architecture would have required a lot of analog building blocks with a lot of mixers, filters and amplifiers.  A lot of this can be replaced by having a very high-speed ADC.      

The advantage here is that you reduce complexity, reduce board area and reduce power consumption while adding a lot more flexibility into the system.    

EE TIMES: Is there any technology development that has enabled this leap in performance or is it a combination of factors?

McCormack: What has really enabled this development is the architecture that we have used at National.  It is quite a unique architecture.  It is not proprietary to National but we have been working with this folding and interpolating architecture for ten years now and we have configured and improved upon it.  We have a number of patents for calibration techniques with this architecture that allows us to get very, very high speeds and we are now up to 12-bit resolution.  So this has given us leadership in the market where maybe our competitors are not using this architecture or haven't the expertise to take advantage of this architecture.     

Of course, to get these very high speeds you can time interleave multiple converters.  One competitor has interleaved four 550 MSPS ADCs to get to 2 GSPS but this is quite a complex solution.  It is difficult to design this at board level and it consumes quite a lot of power.  In half the board area (which has cost implications) we can achieve almost twice the speed and the power consumption is half.  And we have one chip compared to four so we offer a lot of advantages for designers. 

EE TIMES: What applications for European designers will this product be useful for?

McCormack: I see the ADC being definitely applicable in the communications side.  We are talking microwave backhaul, satellite communications.  Even on the optical with fiber coming into a home there are opportunities for using such a high speed ADC.  In Europe there are also apportunities with a lot of high end industrial test and measurement type of equipment including everything from digital oscilloscopes and spectrum analyzers through to scientific equipment for mass spectrometry and telescopes.  Everything that requires a wideband ADC.    

I see a better fit in Europe for the high speed ADCs in military comms and industrial test instrumentation.      

EE TIMES: Where did the development work take place for these new ADCs?

McCormack: These products were developed in Germany.  We have a design center in Munich. For all the ultra high-speed ADCs they were all developed there.   We have two wafer fabs.  One is in Scotland and the other is in the US.  And we have test and assembly in China.       

EE TIMES: Are there any architectures that will be helped by the development of this high-speed ADC?

McCormack: What we are finding is in terms of enabling new architectures we are seeing a move towards to reducing complexity.  So instead of developing a radio in several stages.  On a radio you have the antenna front-end and then generally what has been required in the past is several stages of IF stages.  So you mix this down to a first IF which requires a certain numbers of filters and amplifiers and a mixer.  Then you mix this down to a second IF where you need several more components.  The reason for doing this is because the ADCs were not fast enough or didn't have enough bandwidth to sample the RF signal close to the antenna.  The new architectures we are enabling are really a much less complex system where you remove all these stages of analog signal processing and you sample the signal much closer to the antenna.   So you don't need as many mixers and probably in a lot of applications you don't need any mixers because by sampling the signal close to the antenna you greatly reduce the complexity of the architecture.    

Essentially, you have gone from a hardware-defined architecture to a more flexible software-defined architecture.    

There is much more flexibility with SDR.  When you can digitize the whole bandwidth and do your channel selection digitally this makes your system become very flexible.  If you are doing the channel selection with only analog components then you have a fixed frequency to plan and you have one mixer or NCO for each frequency or a tuner and the cable set top box and it is not very flexible when you want to scale upwards.  So by doing this in software then it is more flexible.  But for software you need a very wide bandwidth component, such as an ADC.

An example is with the LIDAR laser range measurement systems which are used in many industrial and military applications.  With laser measurement systems the accuracy of these is determined by the sampling speed of the ADC.  If you can increase the speed by three times then you have three times more accuracy of the distance measurement.  You are enabling highly accurate measurement equipment by relating it s performance to the sample speed of the ADC.         

In, say, a cable set top box you can replace all the tuner and front end with just one ADC.  This offers significant improvement in board area utilization, power consumption and reductions in the number of components and complexity is reduced obviously.

With applications such as point-to-point radio links and military radar and you can also see the benefits of SDR.  You are eliminating components, reducing board area and adding digital programmability which increases the flexibility.  This is the type of architecture you are enabling with this type of converter which has not really been possible because this type of sample rate at this resolution has not been available until now. 

EE TIMES: Would you say this product is trying to put analog engineers out of business?

McCormack: On the one side you are replacing a lot of analog components but on the other side it puts tough requirements on the few analog components on the front end.  For example, the wideband amplifiers and particularly the clock circuitry. So you still need a lot of analog expertise to get the right level of performance from these ADCS.  The front end amplifier stage and particularly the clock have to be very well designed.  You cannot still rely completely on having a digital design you still need analog expertise.    

National are still very much in the analog business.  We are designing the other blocks – the wideband amplifiers and the clocking parts as well as the digital variable gain amplifiers that match up to the front end here.  You still need your analog designers to get the most out of the systems.    

EE TIMES: So in summary why should a designer opt for using the new ADC?

McCormack: This is really a revolution in speed.  We have pushed the boundary in getting the speed up to 3.6 GSPS in one chip at 12-bits.  It allows the possibility for this much wider bandwidth which is very useful in radio applications but also useful in time domain applications like oscilloscopes. 

The sample rates and the bandwidth are the main things.  When you talk about ADCs your sample rate is really key because that tells you how much bandwidth you can sample instantaneously.  So the higher rate you can sample this opens up doors to new architectures and new applications. 

Sample rate is key and we are going up to sample rates of 3 GSPS which is miles ahead of what's available today.  Today you can only do 1 GSPS at 12-bits now we have pushed that the whole way up to 3.6 GSPS which would have been thought impossible a few years ago.  This allows you to do a bandwidth instantaneously at 1.8 GHz which is huge and combining that with 12-bit dynamic range means you grab the attention of the communications market because with this much resolution you can do really useful work in communications systems, in military radar systems and in high-end test equipment.

There is also the fact you can simplify architectures by eliminating and reducing components, reducing board area.  There are also a lot less thermal problems and board design complexity.  There is also the benefit that it offers low power consumption because this is a pure CMOS technology.


About Paul McCormack

Paul McCormack is the Marketing Manager for National Semiconductor's High-speed product group and is based at the company's European Headquarters in Furstenfeldbruck near Munich.    

McCormack has been with National since 2001, focusing primarily on applications requiring wide-band data converters, amplifiers and frequency synthesisers.    

McCormack has a masters degree in Electrical and Electronic Engineering from the Queens University of Belfast.

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