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Analog EDA

Accelerating the time to IC layout

With the move to nanometre geometries, IC design is becoming considerably more complex and time consuming.  At the same time, analog content is increasing, reflecting strong growth in wireless and sensing technologies, and driven by the consumer, medical and automotive industries.  Market research indicates that although analog circuitry takes up only 20 percent of the area of today's modern mixed signal devices, it is likely to account for some 80 percent of yield loss.

The critical issues here are that due to the complexity of the design and the dramatic increase in process related design rules that have to be considered, mixed signal design, and especially full custom design, is leading to more errors and performance related problems.  Manual design and layout is no longer viable, yet automation in the analog design world remains difficult, and is often an anathema to analog designers.       

European expert panel
The quandary of the analog IC design bottleneck was the focus of a panel session at the recent GSA & IET International Semiconductor Forum, which took place in London in May 2010.  The Global Semiconductor Alliance together with the UK's Institution of Engineering & Technology joined forces to highlight and discuss European trends in semiconductor development.  This year's program focused on leveraging and maximising European expertise in analog/mixed-signal, wireless/portable, and low-power applications.    

From the foundry community was Doug Pattullo of TSMC Europe, who said: “Analog design is now dominating the critical design path despite being only a fraction of the overall chip content.”  Pattullo quoted data from IDG which estimates that 80 percent of all ICs already contain at least 20 percent analog/RF circuitry.  “TSMC's wafer forecast shows mixed signal/RF SoCs growing at 40 percent CAGR,” explained Pattullo.

Pattullo emphasised that the key concern for all parties now is time to profit, commenting: “The drive to reduce system cost and power remains imperative, and mixed signal/RF and analog design remains absolutely critical to reducing cost.”

Pattullo sees the troublemakers as increasing Spice/layout effects, shrinking supply voltages and higher cost per mm² of silicon.  

In terms of finding a solution, Pattullo commented: “We all need to re-assess design tools and practices to ensure we can achieve right first time design in a reasonable timeframe.”  In Pattullo's view, new and improved models, tools and support are required, and importantly, early collaboration (i.e. before the design start) is key.  Pattullo added that different circuit architectures and a digital centric approach is also required.  

This final point was central to the panel contribution from Peter Frith, Chief Technical Officer of Wolfson Microelectronics, representing the fabless mixed signal semiconductor sector. 

Frith pointed out that the inevitable shift to smaller geometries and correspondingly lower voltages, has been steadily creating design challenges in the analog domain for some years. 

Frith said: “Increasing digital signal to noise ratio (SNR) by 6dB requires just one extra bit – that's cheap!  Increasing analog SNR requires twice the area and twice the power – that's not cheap!”  In addition, Frith explained that halving the signal swing at the same noise, worsens analog SNR by 6 dB. 

“Digital circuits can tolerate this, analog cannot,” stated Frith. To halve the noise requires that impedance is reduced to a quarter which in turn demands four times the current.  “As a result, net power consumption doubles!” 

Frith suggested that part of the solution is to replace analog functions with digital circuitry wherever possible – an approach he dubbed: Thick digital, thin analog. 

The impact in design involves the use of more A to D converters (ADCs) as every analog input is immediately digitised, more D to A converters, with at least one for each signal output, and more on-chip digital signal processing.  Such techniques can reduce the number of analog blocks in a design by half, Frith maintained.  

To resolve the signal swing problem as supply voltages reduce, Frith recommended adding integrated charge pumps. 

“This can double the supply voltage when required, yet can also generate efficient reduced supply voltages when low level signals are output, thereby saving power, ” said Frith.

The difficulty is accommodating significant voltages and currents on processes designed for low power and voltage. 

“Sometimes it makes sense to simply off-board these incompatible parts,” Frith said.  Wolfson has found that applying these techniques as the design moves to the next technology node increases the digital gate count, but retains the same analog/digital area split, especially as analog blocks do not scale well as geometries reduce.  In terms of yield, the company claims a digital yield loss representing 30 percent of fails, and within the analog yield loss, about 10 percent of fails are due to leakage or mismatch, while 60 percent are due to THD, SNR or output drive issues. 

IC layout services, design consultancy and training company, IC Mask Design, concurred that analog design and layout is still largely a manual task.  “The full custom layout process is virtually the same today as it was a decade ago!” commented Ciaran Whyte, chief technical officer. “The quality and speed of layout is heavily dependent on the expertise of the engineer.”  

Whyte has found that there are serious discrepancies in design approach, not only between one company and another, but even between design teams within the same company. It is this inconsistency of approach and variable quality of analog layout that creates the biggest problems at fabrication.  Typical quality issues found by fabs are poor matching and overlooked stress relief errors.   

From Whyte's perspective there are two barriers to better quality analog design layout: Lack of education on laying out to new technology nodes, and EDA tools which have generally not provided a real solution, or have been slow to be adopted.     

Accellerating analog layout
Providing the EDA vendor viewpoint on the panel was Ciranova, with tools focused on mixed signal circuit design applications.  Ross Addinall, Europe Technical Director confirmed that the nub of the problem is that with ever increasing complexity, the impact of layout on circuit performance must be considered as early as possible.

 “At advanced nodes, design rules are becoming more complex and more numerous.  In consequence, layout takes a long time, and circuit designers are working without considering parasitic effects,” said Addinall.

As a result, Addinall said, there is a high probability that circuits will need to be redesigned and the layout reworked. “The time to completion becomes unpredictable, which is unacceptable.” 

The solution, Addinall believes, is to get to layout faster to allow early analysis of the extracted design. The time from schematic to layout has to be accelerated, with simulation only after parasitic extraction.   

This requires a change in CAD methodology to accelerate the manual layout process.  The new design flow: schematic to layout including extraction, then simulation, reiteration (as necessary) then verification, replaces the existing process of  schematic, simulation, reiteration, layout and verification (including extraction). 


To support this new methodology, IC design software must feature robust device layout generators, correct by construction placement tools and an integrated router, to enable early analysis and characterisation. 

Although schematic-driven layout has been tried before, quality was not good, lacking the input of the layout expert.  In addition, placement was still manual and therefore time consuming and error prone.  Further, the tools were unable to handle efficiently the huge number of constraints that come with the latest process nodes, effectively negating any benefits of automation. 

But there is a new generation of tools emerging from a number of innovative vendors.  Tanner EDA, for example, has introduced Version 15 of its HiPer Silicon IC design suite providing a complete analog design flow, from schematic capture, circuit simulation, and waveform probing to physical layout and verification.  A key new feature is HiPer DevGen, a tool that enables device and structure generation specifically to accelerate analog layout by automatically generating common structures.   

Developed in conjunction with IC Mask Design, allows the creation of T-cells for CMOS technologies, applies matching techniques to address common processing artifacts, such as current mirrors, differential pairs and resistor dividers.  Rather than attempting to completely automate analog design, HiPer DevGen accelerates the most time–consuming aspects of the layout process, as well as the tedious, repetitive aspects.   


The tool itself incorporates expert knowledge to better understand the technology and matching requirements of commonly used structures.  It then automatically generates the basic building blocks of analog layout with these requirements taken into account. HiPer DevGen is fast and easy to use with techniques to set up basic default values, with tick boxes for options such as guard banding or stress relief, thereby meeting the requirements of 90 percent of analog designs. 

The tool can be used by circuit designers to annotate the design, set certain constraints and highlight parameters or properties.  For example, engineers can prioritise parasitic performance over matching requirements or highlight critical matching concerns.  Meanwhile, layout engineers have complete freedom to lay out and place and route the structures generated.  With constraints and design rules pre-set, the layout experts can concentrate on the critical areas requiring manual intervention.  

For accurate layout-to-circuit extraction, HiPer PX allows the designer to model accurately interconnect parasitic effects and crosstalk. Successful RF IC tapeouts are assured by avoiding overdesign to provide safety margins, while eliminating laborious and potentially inaccurate manual estimations of parasitics.     

Little change
To take best advantage of the accelerated layout benefits afforded by tools such as HiPer DevGen and HiPer PX, some change of methodology and mindset is necessary. Tanner's tool  was designed to be implemented with little change to existing design flows. It works with unmodified schematics, uses netlists produced for schematic driven layout (SDL) and also accepts input directly from S-Edit, Tanner EDA’s schematic editor.  

Analog automation has long been a dream of EDA vendors, defied by the inherently unstructured nature of analog circuits, and to some extent, the resistance of analog engineers.  But certain functions can be successfully automated, provided there is true interaction between the schematic and physical design tools, and respect of the knowledge of the analog experts.  Automation can accelerate but will not fully replace manual layout creation.

About the author
Paul Double is EDA Solutions founder and CEO. After gaining a B.Sc. Hons. in
Physics and Electronics at the University of Warwick, UK, Double started his
career in IC Design with Phillips Semiconductors (now NXP), eventually
moving into product management.

Double then spent eight years in Design Consultancy and EDA Software sales management, first with Rood Technology, then later with Acapella. It was at Acapella he first gained experience with the Tanner tools and came to fully appreciate the benefits of MOSIS MPW services. In 2001 Doublel founded EDA Solutions to further the interests of both Tanner and MOSIS throughout Europe. In this time Tanner¹s sales in Europe have increased almost 400 percent.

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