Bridging the Divide (Part 1): DAC Introduction
June 21, 2010 | Paul Buckley | 222900832
Bill McCulley, Applications Engineer, National Semiconductor, examines basic DAC operation, key definitions, together with common DAC topologies.“The best of what we are and hold as true: Always it is by bridges that we live."
Philip Larkin, British poet
Our world is not a digital environment of absolutes. The electrical signals of the real world are not made of logical highs and lows, or zeros and ones. These signals are analog and they meander within a range of voltages or currents.
The purpose of the Digital to Analog Converter (DAC) is to convert digital data into an analog signal. The digital data may originate from a microprocessor, ASIC, or FPGA, but at some point requires conversion to an analog signal to have impact on the real world. Whether the system uses an audio amplifier, an LED indicator, or a motor driver, the final signal will be analog in nature.
The DAC serves as that bridge to transfer a digital signal into the analog domain – and hopefully ends with an accurate and true representation of the signal! As an important part of many electronic systems, it is good to learn about the fundamentals of the DAC.
This first article covers basic DAC operation and key definitions, along with common DAC topologies. The second article will discuss the implementation of DACs, along with issues such as errors and noise. The final article will review two important DAC applications: calibration and motor control.
Since the time of the Nyquist-Shannon sampling theorem, engineers have developed and used DACs, but it is only the past 25 years that monolithic DACs have become widely available. According to the Nyquest-Shannon sampling theorem, any sampled data can be reconstructed perfectly - provided it meets bandwidth and Nyquest criteria (Ref 1). So, with proper design a DAC can reconstruct sampled data in your application with precision.
Digital-to-analog converter operation
Figure 1 is a diagram of a 4-bit parallel-input DAC (Ref 2). With a 4-bit DAC, there are 24= 16 possible input data codes as shown on the table first column. For the input data code, DACs may use straight binary or two’s complementary system (Ref 3), with straight binary being most common. DACs have an analog reference (VREF), along with power supply (VA), and an analog output. In many cases, the reference and supply voltages may be the same, and therefore the DAC will have a single pin for both functions. Also, the reference can be a voltage or a current, depending on DAC design.
The DAC multiplies the input data code by the reference to generate the analog output. (So the DAC is the opposite function of ADC, which is a divider to convert an analog input into digital bits.) The DAC can have a voltage or current output, depending on design. Current output DACs are particularly well suited for high frequency applications, in applications that may require more precision that can be achieved with on board current-to-voltage conversion. Also, some types of DACs use bipolar (positive and negative) instead of unipolar structure, which can be used to create two-quadrant and four-quadrant Multiplying DACs.
For this tutorial we will focus on unipolar voltage-output DACs from which you can easily grasp the theory of other DAC structures.
Continuing with Figure 1, the Least Significant Bit (LSB) is the rightmost bit of the data code and represents the smallest value in a digital code and the Most Significant Bit (MSB) is the leftmost bit of the data code and also represents the half-scale value. As you can see on the table, the LSB (0001b) represents 0.3125 V. The LSB value is determined by the basic equation below:
In most DACs, the gain (G) is 1, which reduces the equation to VREF/2N. In an ideal DAC, each additional bit will increase the output voltage by one LSB. In this example, the value of one LSB is 0.3125 V, which is the smallest increment the DAC can resolve. Multiplying the LSB value and the Data Input Code (DIN), the basic transfer function can be expressed as shown in Equation 2:
With a DIN of 1111, the DAC output is shown in Equation 3. As shown, the maximum output value in this example is one LSB (0.3125 V) below the voltage reference (5 V).
As you can see, the output voltage can rise to only 1 LSB less than the full scale voltage. This is common among many DACs, but some DACs are designed specifically to allow maximum output voltage to reach full-scale voltage.
Now, what is the key factor for a DAC for properly representing an analog signal? It is the DAC resolution or the ‘granularity’ of the signal it can produce. On Equation 1, you can see the LSB value is inversely proportional to the number of bits (N) and directly proportional to VREF. So, an increase in the number of bits will decrease the LSB value. The result is an increase in DAC resolution and a better granularity for the signal.
Figure 2 shows an example of a ‘real world’ sinusoidal waveform, along with examples of a 4-bit and 6-bit DAC. The DAC outputs should truly be represented by discrete points mathematically. But due to delay times, the output of a DAC in operation will resemble the well-known ‘stair step’ signal as on an oscilloscope. It should be noted that you can achieve similar improvement in resolution by decreasing the reference voltage. However this will result in a lower full-scale output range, since the maximum achievable output is constrained to VREF - 1 LSB.
Figure 2 – Sinusoid and DAC resolutions
Key terms and definitions
The basic operation of a DAC is easily understood, but the terms used among semiconductor manufacturers can appear confusing and even contradictory. So it is important for a designer to understand the meanings of key parameters seen on most DAC datasheets for your application.
Monotocity is the condition in which the DAC transfer function’s slope does not change. Monotocity is an indication of linearity of the DAC.
Resolution refers to number of bits, and with the analog reference, determines granularity of the signal conversion. Resolution also refers to the output value representing one LSB.
Setting Time (Figure 3) is the time from a change in the input code until the DAC output signal is generated and remains within specified output tolerance or characterization range. It is important to know that the tolerance may differ among vendors, and can have a large impact on specified settling time!
Output Glitch is the energy injected into the analog output when the input data code changes. The amount of glitch energy depends upon how many bits are changing from high to low or low to high. The output glitch occurs at the major carry (e.g. for example, changes from 0111b to 1000b) but it can also occur during other transitions.
Offset Error, also referred as Zero Code Error (ZE), is the difference between the actual and ideal output when the input code is zero. So, if the zero code error for a part is specified as 1.1mV, and the input data word is 0000b, then the output voltage will be 1.1 mV an offset error above 0 V.
Full Scale Error
Full Scale Error (FSE) is the difference between the actual output voltage and the full scale code value as is loaded into the DAC.
Gain Error (GE) is the deviation from the ideal slope of the DAC transfer function. It can be determined from the Zero and Full-Scale Errors as GE=FSE-ZE.
DNL & INL
Differential Non-Linearity (DNL) describes the error in step size and is the measure of the maximum deviation from the ideal step size of 1 LSB. Integral Non-Linearity (INL) is a measure of the deviation of each individual code from the straight line through the input to output transfer function. Both these terms merit a full tutorial in their relation to DACs and ADCs, so a link is available at the end of this article. (Ref 4).
String DACs are among the most popular DACs and have many variants available. These include the basic Kelvin Divider, binary weighted, digital potentiometer-focused, segmented-string DACs among other types.
The Kelvin Divider, also referred as a string divider, is the simplest and very common DAC topology. On Figure 5, this topology uses internal resistors with switches at each node and a logic block for decoding the binary inputs. An N-bit DAC will contain 2N resistors and 2N switches. This topology has a voltage output, and is monotonic by its nature and linear in using exactly matched resistors.
A major disadvantage for this topology is its relatively high output impedance. Most vendors add an internal amplifier as an output buffer to create a low impedance source for follow-on circuits. There are a large number of resistor/switches required, depending on the resolution of the DAC. A 4-bit DAC only requires 16 resistors/switches; while a medium resolution 12-bit DAC will require 4096.
Process improvements have made this topology very common in DACs up to 12-14 bits. To the right of the string divider diagram, you can see the DAC121S101, which integrates an amp buffer and uses Serial Peripheral Bus (SPI) interface for input data and control.
Figure 5 – Kelvin Divider and 12-bit String Divider - DAC121S101
R-2R Ladder DACs are another very common topology. In Figure 6, this voltage output DAC uses two values of resistors, with a ratio of 2-to-1. As seen below, the number of resistors is much reduced compared to string DACs. Any R2-R DAC needs just 2·N resistors – making the job of trimming the resistors values easier. So, a 4-bit DAC requires only eight resistors, and an 8-bit DAC will require just 24 resistors. To the right of the R-2R diagram is a diagram of DAC0831, which includes parallel input code register, along with support function blocks for microprocessor interfacing.
Figure 6 – R-2R Ladder
The R-2R ladder can either be designed with a voltage or current output. A key benefit of using the voltage output is the constant output impedance which makes it easier to interface with a buffer amplifier on the output. Much like string DACs, there are several variants of the R-2R ladder topology that have been developed as process technology improves.
Multiplying DACs (MDAC) are a variant based on the R-2R ladder. Since the R-2R switches can be done with CMOS switches, it is easy to construct a ladder to use bi-polar signals on the input. Using bipolar – positive and negative – signals on the input, the topology can be designed to enable two-quadrant and four-quadrant MDACs. These MDACs are often used as a Variable Gain Amplifier, but there also many unique applications beyond that use.
Segmented DACs are a topology which mixes or cascades several other DACs architectures whether string or R-2R ladder. These specialized DACs are commonly seen in high speed video or audio systems in which the reconstruction of a signal demands performance across a wide range of voltage or frequencies.
Sigma Delta (Σ-Δ) DACs are a ‘relatively’ new topology and operate similar to Sigma Delta ADCs. This DAC circuit takes input data at a low rate, adds zeros at a high rate into the data stream, and then filters over time at a high rate. The data stream is then passed through a Σ-Δ modulator which converts the data to a bit stream, followed by a 1-bit DAC which switches between equal and negative reference voltages. Sigma Delta DACs (and ADCs) have gained popularity due to its high resolution and very good DNL. Sigma Delta DAC applications include calibration, audio, and voice band systems. It is limited in terms of bandwidth, so it is not used among high speed applications.
In electronic design, DACs play an important role in converting digital data into an analog signal. DACs can be found in calibration systems, motor control, factory test equipment, audio systems, measurement equipment, and control systems, among many others. But as important as the DAC is, the design engineer should remember it is just one part of a system which can include a processesor and memory, power supplies, analog circuits, and other mixed-signal devices. The architecture is what ties these functional blocks together. What affects your DAC circuit (such as noise and error) will also affect the other blocks of your architecture. With that in mind, the next article will cover how to design with DACs.
(Ref 1) H. Nyquist, "Certain topics in telegraph transmission theory", Proc IEEE, Vol. 90, Feb 2002 (Reprint); http://www.loe.ee.upatras.gr/Comes/Notes/Nyquist.pdf
C. E. Shannon, "Communication in the presence of noise", Proc IEEE, Vol. 86, Feb 1998 (Reprint); http://www.stanford.edu/class/ee104/shannonpaper.pdf
(Ref 2) Modern DACs use interfaces like Inter-IC Bus (I2C) or Serial Peripheral Interface (SPI), which allow for small packages and fewer pins. In this tutorial example, a legacy parallel input DAC is used.
(Ref 3) Tutorial on signed binary numbers – http://en.wikipedia.org/wiki/Signed_number_representations
(Ref 4) Nick Gray’s excellent tutorial on ADC & DAC errors (registration required) - http://www.national.com/AU/design/0,4706,179_0_,00.html
About the author
Bill McCulley is a Staff Applications Engineer for National Semiconductor and covers all broad market applications for the Americas region. He is based in National Semiconductor's Customer Support Center in Texas. Bill McCulley has been with National for nearly five years, and has held positions as an engineer for technical marketing and applications engineering. Bill McCulley holds a BSEE (Electrical Engineering) degree, and a minor in Spanish (Latin-American dialects) from the United States Naval Academy in Annapolis, Maryland.
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