New features in Allegro 16.6 Package Designer and Cadence SiP Layout include open cavity support for die placement, a new wirebond application mode that improves efficiency, and a wafer-level-chip-scale-package (WLCSP) capability delivering the industry’s most comprehensive design and analysis solution for IC package design.

“The increasing demand for high-end and next-generation IC package designs is driving us to use innovative design tools and techniques to meet our customers' needs,” said Choon Heung Lee, Amkor’s corporate vice president, product management. “Based on our testing of Allegro Package Designer and Cadence SiP layout, we expect Cadence's IC package design solutions to help us meet the growing list of challenges in advanced package design.”

Cadence has built functionality into its Allegro tools that address challenges associated with IC package implementation for small/ thin consumer electronics products. The Allegro 16.6 solution supports a new database object for open cavity placement that provides enhanced capabilities, such as DRC and 3-D viewing, to support die placement within a cavity of the package substrate. A new intuitive wirebond application mode improves throughput by focusing specifically on the wirebond process. The Cadence Allegro suite enables a highly efficient WLCSP flow by reading and writing more concise GDSII data. A new advanced package router, based on Sigrity technology, accelerates the substrate-level interconnect implementation of a package. Lastly, package assessment, model extraction, signal and power integrity analysis, also based on Sigrity technology, have been integrated into the Allegro 16.6 solution. This makes the analysis and signoff portion of the IC package design flow much easier and quicker.

“The design challenges of small/thin consumer electronics products continue to drive the advancement of the Cadence leading package design tools,” said Keith Felton, product marketing group director for PCB and IC packaging, Cadence. “In addition to offering IC package solutions with a physical design perspective, Allegro now enables customers to analyze and validate high-performance, low-power devices for electrical compliance as well. This improves design time and speeds time to market.”

The new enhancements in Cadence Allegro enable a more predictable and efficient design cycle. Additionally, improvements to the Allegro co-design flow create better collaboration with both chip and PCB design teams resulting in improved system-level performance and overall system costs.

Availability

Allegro release 16.6 IC package solution is scheduled to become available in Q4, 2012.

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