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Cadence unveils high-performance, low-power design IP to supportLPDDR3 memory standard

March 22, 2012 | Paul Buckley | 222903213
Cadence unveils high-performance, low-power design IP to supportLPDDR3 memory standard Cadence Design Systems, Inc. has added design intellectual property (IP) for the LPDDR3 mobile memory standard to the companyís design IP portfolio. Designed to provide the high bandwidth and low power consumption required by smartphones and tablets, the Cadence LPDDR3 memory IP solution includes integrated controller and PHY support, virtual prototyping, verification IP and Allegro design-in kits to accelerate implementation and reduce design risk.

Cadence's highly configurable design IP allows the LPDDR3 standard to be combined with others in a single controller and PHY to enable SoCs that support multiple memory standards, making one design usable by multiple markets.
“To keep pace with the growing processing capabilities of today’s smartphones and tablets, SoC designers must support memory standards that are evolving just as quickly,” said Marc Greenberg, director of product marketing, SoC Realization Group, Cadence. “At Cadence, our goal is to enable early access to these standards by offering customers a broad range of high-performance, low power design IP standards, like LPDDR3, so they can quickly integrate the standard into new SoC designs.”

As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption.

In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.

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