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Clocking requirements for high speed data converters

August 18, 2009 | | 219400342
There are several key performance metrics required for clocking circuits in wireless infrastructure, broadband and instrumentation, such as low phase noise and jitter, accurate frequency translation and jitter filtering. This article discusses the clocking technologies required.
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Wireless infrastructure, broadband and instrumentation applications generally require very high performance clocking circuits. The primary components being clocked in these systems are high speed data converters. There are several key performance metrics required for these clock circuits such as low phase noise and jitter, accurate frequency translation and jitter filtering capability. This article will discuss the clocking technologies required.

Basestation transceivers, broadband modems and high-end instrumentation usually require analog-to-digital converters (ADCs) and/or digital-to-analog converters (DACs) with high dynamic range, high sampling rates, or both.

The requirements on a given converter will be determined by the overall system specifications and architecture. The spectral purity of the sampling clock supplied often has a significant impact on the performance achieved.

For example, consider the wireless transceiver circuit diagram shown in Figure 1. The clock generator provides clocks for the ADCs and DACs, and also distributes clock signals to several of the other circuit blocks.

Figure 1.Transceiver block diagram

A key metric for ADCs used in radio receivers is Signal to Noise ratio (SNR). This will impact how accurately an ADC can sample signals. Ideally an ADC should be able to convert small analog input signals into accurate digital representations with a high degree of resolution. In radio terms, an ADC's SNR will determine the Minimum Detectable Signal (MDS).

Theoretical SNR based on the quantization noise for an N bit converter is given by:

Equation 1: SNR = 6.02(N) + 1.8db

So for a 14bit converter the best achievable SNR would be about 86db.

In Intermediate Frequency (IF) sampling architectures, such as that shown in Figure 1, the requirements on clock jitter can be stringent. In fact, the quality of the clock provided to the ADC is often the limiting factor in the system SNR (Equation 2).

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