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Low-power design; approaches, techniques and tools

March 21, 2008 | | 206905603
Check out this excerpt from "Power Management In Mobile Devices," which provides an overview of the challenges facing designers of feature-rich mobile devices that call for smaller form factor and lower cost.
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The following text is excerpted from Chapter 3 of the book Power Management in Mobile Devices by Findlay Shearer. Printed with permission from Newnes, a division of Elsevier, copyright 2008. For more information about this title, visit www.elsevierdirect.com.

The book, for technical managers, software developers, hardware designers, and manufacturing engineers in the mobile device industry, provides an overview of the challenges facing designers for feature-rich mobile devices that call for smaller form factor and lower cost. It follows with in-depth coverage of energy-optimized software, batteries and displays, power management ICs (PMICs), and system-level approaches to energy conservation.

If you order a copy of this book by June 1, 2008, you will receive a 20 percent discount. Click here and make sure to type in 92351 when ordering this book. Or call 1-800-545-2522 and mention 92351.

Low Power Design Techniques
Dynamic Process Temperature Compensation
A common engineering philosophy when designing a System-on-a-Chip (SoC) is to insure that they perform under "worst-case" conditions. Worst case in semiconductor manufacturing applies to very high temperatures and variations in the manufacturingprocess; transistor performance varies in a predefined range of parameters. Thus, some SoCs from the same wafer lot are capable of supporting higher operating frequencies (best case fast process) or lower frequencies at the bottom of the predefinedperformance window (worst case slow process) at the given voltage (Figure 3.1).

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