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Analog EDA

Moving to SystemC TLM for design and verification of digital hardware

May 21, 2013 | Stuart Swan, Qiang Zhu and Xingri Li | 222905117
Moving to SystemC TLM for design and verification of digital hardware Stuart Swan, Qiang Zhu, Xingri Li, Cadence Design Systems, Inc. consider the issues faced when moving to SystemC TLM for design and verification of digital hardware.
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Introduction

Design and verification of new digital hardware blocks is becoming increasingly challenging. Today, designers are confronted with a host of issues, including growing design and verification complexity, time-to-market pressures, power goals, and evolving design specifications.

To tackle these challenges, customers are beginning to make a significant change in design methodology, by moving to SystemC transaction-level models (TLM) as the design entry point, and by leveraging high-level synthesis (HLS) in combination with IP reuse. This article presents our experience in working with Fujitsu Semiconductor Ltd. to adopt this new methodology using Cadence C-to-Silicon Compiler on a data access controller design, and presents the very promising results they reported at a recent C-to-Silicon user group meeting in Japan. The selection of the design, modeling work, and results analysis described in this paper were performed by Fujitsu Semiconductor with some assistance from Cadence.

Motivation for Moving to a New Approach

While Fujitsu Semiconductors design groups are very experienced at design, verification, and synthesis at the register-transfer level (RTL), they have found that this approach has many limitations that have become an increasing problem as design and verification complexity increases.

Some of the key limitations with the RTL entry approach include:

  • Very limited ability to perform algorithmic and architecture exploration, and thus a very limited ability to optimize area, power, and performance. This is because RTL designs are too detailed, and are not functional soon enough, to enable this type of exploration.
  • Limited ability to build configurable models that can be reused in different environments. This is because the detailed structure of the design at the RT level is largely fixed.
  • Inefficient verification. This is because the complexity of the RTL makes for increased chances for bugs, and it also makes debugging and isolating problems more difficult.
  • Long design and verification times, delaying time to market.
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