Implemented on a 65-nm process technology, the Intelli DDR3 PHY+DLL solution enables RDC to meet 1.6 Gb/s data rates for DDR3 interface solutions, consuming less power and requiring a smaller area compared to traditional analog solutions. The Intelli DDR3 PHY+DLL solution offers RDC a semi-custom approach, where the PHY macro dimensions can be tailored to optimize the memory subsystem to meet particular market applications.

RDC is targeting one of the highest growth segments of the consumer electronics market. According to research firm Strategy Analytics, net-based application shipments jumped 79 percent last year to 30.2 million units and the market is poised to continue growing this year. The Milton Keynes, United Kingdom research firm said that the North American and Western European regions propelled the market's growth. In the United States, carriers including AT&T Mobility, Verizon Wireless and Sprint Nextel, have begun subsidizing net-based applications (with the purchase of a two-year mobile data plan) and carrying the devices in their retail outlets. Thus, along with smartphones and data cards, net-based applications with built-in, wide-area wireless capabilities have helped fuel mobile data traffic growth. The carriers have been selling net-based applications for between $150 and $200 when paired with a two-year data plan contract.

"We are thrilled that RDC Semiconductor chose Virage Logic for this net-based application System-on-Chip (SoC) design," said Dr. Yankin Tanurhan, vice president and general manager for Virage Logic's Processor, SoC Infrastructure, Application Specific IP (ASIP) and NVM Solutions business units. "One of the attractions of this solution beyond performance, power, and area, is that the Intelli DDR2/3 PHY+DLL includes system-level knowledge to deliver automated capabilities that can signal potential variations in silicon, package and/or board design, and manufacturing."

"The Virage Logic solution was particularly advantageous for RDC because we had to meet a tight time-to-market window," said Jacky Tsai, manager, marketing department at RDC Semiconductor Co., Ltd. "Virage Logic's DDR2/3 PHY+DLL met the size, power, and performance requirements for our next-generation SoC and it was implemented on a 65nm process, which was the foundry and process node that our engineering team had qualified for this design. This perfect combination of factors made our choice very easy."

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