As process geometries continue to shrink beyond 40 nm, it becomes imperative for parasitic extraction to understand and accurately model and predict the impact of substrate, inductance and mutual inductance on the performance of a chip.

Cadence QRC Extraction is the first to be certified at advanced nodes by leading foundries. Along with feature-rich advancements in leading-edge process modeling and integration with the Virtuoso Custom IC and Encounter Digital Implementation Platforms, QRC is the tool that provides a seamless single parasitic solution for digital, custom, RF, memory, analog, mixed-signal and substrate extraction. STMicroelectronics' customers and design centers easily realised the differentiated productivity and silicon predictability benefits.

"We evaluated Cadence QRC Extraction and found it competitive to be included in our 40LP analog/RF mixed-signal/digital signoff design flow. Our customers and designers are bound to benefit from its adoption in terms of higher design performance," said Vincent Varo, CMOS and Derivative PDK Manager, Technology R&D, STMicroelectronics "Our evaluation confirmed that QRC Extraction is able to manage the complexity of advanced 40nm effects with suitable model accuracy, besides its seamless integration with the Cadence Virtuoso and Encounter design environments."

To qualify for the ST extraction flow, QRC Extraction passed a rigorous evaluation involving multiple designs and dozens of criteria. With the successful conclusion of this evaluation, QRC Extraction technology was qualified to be a part of the 40LP methodology widely deployed to ST's design centers developing large-scale, complex digital and analog designs.

Related link: www.cadence.com