"3-D affords the capability of integrating FPGAs with ASICs, with memory with ASSPs, DSPs, MPUs or even with FPGAs from other vendors, thereby boosting system performance by minimizing power, downsizing form factor and lowering BoM [bill of materials]," said Jeff Waters, senior vice president and general manager of military, industrial and computing division at Altera. "The promise of 3-D packaging is so great that Altera is dedicated to surmounting the engineering challenges of silicon interposer fabrication, optimizing resulting signal integrity, solving system integration issues, and managing yield and cost."
Altera is cooperating with TSMC to use wafer scale integration of heterogeneous chip sets with its silicon interposer which can interconnect any number or separate die inside a common package. As a result, ASICs are losing their traditional advantage in high-volume applications, according to Altera.
Traditionally, ASIC had the advantage in both chip size and cost, but at advanced processor nodes now the up-front costs for masks is $10 million and up. In fact, between 2006 and 2008, according to Waters, a three-to-one gap opened between the cost of using an ASIC and using a FPGA, with the tipping point toward FPGA, occurring circa 2009.
"Now FPGA-based designs are outgrowing ASIC-designs by 2X, because it is just too expensive to develop an ASIC except in very high-volume consumer applications," said Waters. "FPGAs are also starting to take over DSP and ASSP applications."
Today, processors with on-chip DSPs have the advantage over ASICs in every dimension except power efficiency. But Water claims that by adding heterogenous processor cores, DSPs, ASSPs and even small ASICs alongside them on same chip, FPGAs are filling the power efficiency advantage of ASICs.
"We call this silicon convergence, because by adding hardware processor cores and DSPs right on the FPGA, as well ASICs and ASSPs, these heterogeneous FPGAs are beating ASICs in all dimensions," said Waters.
For the future, the key challenge to FPGA silicon convergence is