Execute-in-place can be used where insufficient on-chip flash is available and instead of on-chip SRAM which would have to load in pages of program memory from non-volatile storage. Adesto also argues that by using a low-cost but high density flash process for the memory and a simpler CMOS for the logic it is possible to produce tuned performance and scalablity without requiring logic respins.
However, execute-in-place has had issues over speed of transfer over SPI and power consumption that Adesto has attempted to address. As a result Adesto's EcoXiP more than doubles processor performance, lowers system power consumption and reduces system cost compared to standard serial peripheral interface (SPI) devices.
Samples of Adesto’s EcoXiP are available to lead customers now. Adesto is sampling a 32Mbit device at introduction, with a family of densities up to 128Mbit planned for the future.
The steps Adesto has taken are to add a command to the SPI protocol to allow multiple 16byte cache lines to be fetched in response to that one command. The result on a typical 266MHz clocked CPU with a 4 percent cache miss rate and operating over an 8-wire OPI bus (Octal SPI) is a 41 percent speed up in the processor speed, said Adesto.
For existing memory controllers and MCUs that follow the SPI standard this speed up is not available but Gideon Intrater, CTO of Adesto, told EE Times Europe that the company has been working with ten MCU suppliers including market leader NXP and IP provider Synopsys to support this feature.
SPI host controllers for EcoXiP are available from Adesto IP partners including Mobiveil and Synopsys.
The speed up enabled will also reduce power consumption by allowing the CPU to go back to sleep mode sooner. But to address power consumption over the OPI Adesto has provided programmable I/O drivers. Configurable strength IO pins from 1pF to 15pF reduces the power consumed during read operations and allows