The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nm FinFET-based design flow.
The 14-nm ecosystem and chip are milestones of a multi-year agreement between ARM, Cadence and IBM to develop systems-on-chip (SoCs) at the advanced process nodes of 14-nm and beyond. SoCs designed at 14-nm with FinFET technology offer the promise of a reduction in power consumption.
"This chip represents a major milestone for advanced node process technology, achieved through tight collaboration among experts at the three companies,” said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “FinFET designs offer significant advantages to the design community, but also require advanced foundry support, IP and EDA technology to meet the considerable challenges. Cadence, IBM and ARM are collaborating to address these challenges and develop an ecosystem that can support 14-nm FinFET development for a broad range of production designs.”
The chip was developed to validate the building blocks of foundation IP for 14-nm design. In addition to the ARM processor, SRAM memory blocks and other blocks were included that provide the characterization data necessary for foundation IP development for FinFET-based ARM Artisan physical IP.
“Each move to smaller geometry brings new challenges that require deep collaboration among ecosystem leaders in the SoC design chain,” said Dipesh Patel, vice president and general manager, Physical IP Division at ARM. “With 14-n design, many of these challenges center on FinFETs, and our work with Cadence and IBM has focused on answering the key questions about how to make 14-n FinFET design viable and economically feasible.”
ARM design engineers incorporated an ARM Cortex-M0 processor using 14-nanometer FinFET technology built on IBM’s silicon-on-insulator (SOI) technology, which offers an optimal performance/power profile. A comprehensive 14-nanometer double patterning and FinFET support methodology was employed, with engineers using Cadence technology to design