The port comes just four months after the 2014 startup announced reconfigurable FPGA cores for implementation in TSMC's 40nm ultra-low power manufacturing process (see FPGA cores offered for TSMC's 40ULP process). The company is also moving its higher capacity EFLX-2.5K cores from TSMC's 28nm CMOS process to the 16nm FinFET processes.
At 16nm the Flex Logic fabric offers single-stage logic performance at about 1GHz clock frequency under worst process, voltage and temperature conditions. "The optimization is for higher performance," Geoff Tate, CEO and co-founder of Flex Logix, told EE Times Europe. "As we are going after data center, networking and basestation applications."
"In these applications there tends to be less arithmetic and more patten-matching and field-swapping, so we have put more I/O capability and changed the size of the LUT [look-up-table] to a 6-inputs," he added. This contrasts with the previous 4-input design.
Tate said he expects the fabric to be fully validated by TSMC early in 2017 and for customers to be taping out SoCs that include the FPGA fabric in the first half of 2017.
GDS-II of TSMC 16FF+/FFC validation chip expected to complete validation in early 2017. Source: Flex Logix.
The EFLX-100 IP cores can be arrayed to make larger arrays up to 5 by 5 with any combination of Logic and DSP IP cores inter-mixed. This covers from 120 LUTs up to 3000 LUTs. High-level design for the fabric is done using Synplify from Synopsys down to RTL. The EFLX compiler software takes in Synplify netlist.
Next: Reconfigurable data centers