The report was given at the International Electron Devices Meeting 2016 (IEDM) in San Francisco in a special poster session on MRAM (see IEDM: Magnetic RAM debuts as 28nm embedded NVM ).
IMEC claims this is the world's smallest pMTJ and demonstrates the suitability of spin-transfer-torque magnetic random access memory (STT-MRAM) arrays to meet requirements of the 10nm node and beyond for embedded non-volatile memory applications. It also paves the way for high density stand-alone memory component applications, IMEC asserts.
The core element of an STT-MRAM is a magnetic tunnel junction (MTJ) in which a thin dielectric layer is sandwiched between a magnetic reference layer and a magnetic free layer, where writing of the memory cell is performed by switching the magnetization of the free layer. STT-MRAMs exhibit non-volatility, high-speed, low-voltage switching and nearly unlimited read/write endurance.
The pMTJ stack, featuring a free layer and reference layer of CoFeB-based multilayer stacks, was developed on 300mm silicon wafers and the fabrication process is compatible with the thermal budget of standard CMOS back-end-of-line (BEOL) technology, IMEC said. In addition the researchers have integrated arrays of these pMTJ devices into a 1T1MTJ memory cell to build STT-MRAM arrays of 1Mbit with pitches down to 100nm.
"STT-MRAM is a promising memory concept for future technology nodes, but its scalability towards high densities has always been challenging," said Gouri Sankar Kar, the research leader who is coordinating ReRAM, DRAM-MIMCAP and STT-MRAM activities at IMEC. IMEC's research into advanced memory is performed in collaboration with multiple companies including Globalfoundries, Micron Technology, Qualcomm, Sony and TSMC.
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