Startup plans to embed processors in DRAM

October 12, 2016 // By Peter Clarke
Fabless chip company Upmem SAS (Grenoble, France), founded in January 2015, is developing a microprocessor for use in data-intensive applications in the datacenter that will sit embedded in DRAM to be close to the data.

Placing hundreds or thousands of processing elements in DRAM able to perform work for a controlling server CPU could have a revolutionary impact on how data centers are designed. Simulation results have shown a performance increase of factors of 10 to 25 compared with traditional server architectures, the company said. In other words a single server built using Upmem technology and running certain algorithms could perform the work of 10 to 25 servers while consuming less power.

The use of local processing and extreme parallelism has been understood to increase processor-memory bandwidth and reduce power consumption for a long time – it is part of the promise of FPGAs – but delivering such architectures at the system level has rarely happened.

Upmem, thinks it can change that and is developing a RISC processor design codenamed DPU (stands for DRAM processing unit) that is optimized for intensive data processing and compatible with DRAM manufacturing process constraints. DPUs can be used as simple functional co-processing units or as a network co-operating within a massively parallel environment. Typical applications that Upmem claims are suitable for this approach include: real-time analytics, pattern matching, database serving and implementation of artificial neural networks.

The company was co-founded by Fabrice Devaux (CTO) and Jean-Francois Roy (COO) – both formerly of Trango Virtual Processors – and serial entrepreneur Gilles Hamou (CEO). To date the company has been funded by the founders and angel investors.

Jean-Francois Roy, COO and co-founder of Upmem

Building on research work done by Devaux prior to the company's formation the startup has now finalized its RISC architecture and micro-architecture and has prototyped the design. "Our proof of concept was done on a 4x-nm process, and we reached 600MHz [clock frequency]. This is very promising and demonstrated that we will reach 1GHz with a more recent process," Roy told EE Times Europe. The architecture is 32bits and one processor is attached per DRAM bank of 64Mbytes.